fanout of a standard cell in vlsi physical design
-->
Max Fanout of a CMOS Gate:
When it comes to doing digital circuit design, one has to know how to size gates. The idea is to pick gate sizes in such a way that it gives the best power v/s performance trade off. We refer to concept of ‘fanout’ when we talk about gate sizes. Fanout for CMOS gates, is the ratio of the load capacitance (the capacitance that it is driving) to the input gate capacitance. As capacitance is proportional to gate size, the fanout turns out to be the ratio of the size of the driven gate to the size of the driver gate.
Fanout of a CMOS gate depends upon the load capacitance and how fast the driving gate can charge and discharge the load capacitance. Digital circuits are mainly about speed and power tradeoff. Simply put, CMOS gate load should be within the range where driving gate can charge or discharge the load within reasonable time with reasonable power dissipation.
Our aim is to find out the nominal fanout value which gives the best speed with least possible power dissipation. To simplify our analysis we can focus on the leakage power, which is proportional to the width or size of the gate. Hence our problem simplifies to, how can we get the smallest delay through gates, while choosing smallest possible gate sizes.
Typical fanout value can be found out using the CMOS gate delay models. Some of the CMOS gate models are very complicated in nature. Luckily there are simplistic delay models, which are fairly accurate. For sake of comprehending this issue, we will go through an overly simplified delay model.
We know that I-V curves of CMOS transistor are not linear and hence, we can’t really assume transistor to be a resistor when transistor is ON, but as mentioned earlier we can assume transistor to be resistor in a simplified model, for our understanding. Following figure shows a NMOS and a PMOS device. Let’s assume that NMOS device is of unit gate width ‘W’ and for such a unit gate width device the resistance is ‘R’. If we were to assume that mobility of electrons is double that of holes, which gives us an approximate P/N ratio of 2/1 to achieve same delay(with very recent process technologies the P/N ratio to get same rise and fall delay is getting close to 1/1). In other words to achieve the same resistance ‘R’ in a PMOS device, we need PMOS device to have double the width compared to NMOS device. That is why to get resistance ‘R’ through PMOS device device it needs to be ‘2W’ wide.
Figure 1. R and C model of CMOS inverter
Our model inverter has NMOS with width ‘W’ and PMOS has width ‘2W’, with equal rise and fall delays. We know that gate capacitance is directly proportional to gate width. Lets also assume that for width ‘W’, the gate capacitance is ‘C’. This means our NMOS gate capacitance is ‘C’ and our PMOS gate capacitance is ‘2C’. Again for sake of simplicity lets assume the diffusion capacitance of transistors to be zero.
Lets assume that an inverter with ‘W’ gate width drives another inverter with gate width that is ‘a’ times the width of the driver transistor. This multiplier ‘a’ is our fanout. For the receiver inverter(load inverter), NMOS gate capacitance would be a*C as gate capacitance is proportional to the width of the gate.
Figure 2. Unit size inverter driving ‘a’ size inverter
Now let’s represent this back to back inverter in terms of their R and C only models.
Figure 3. Inverter R & C model
For this RC circuit, we can calculate the delay at the driver output node using Elmore delay approximation. If you can recall in Elmore delay model one can find the total delay through multiple nodes in a circuit like this : Start with the first node of interest and keep going downstream along the path where you want to find the delay. Along the path stop at each node and find the total resistance from that node to VDD/VSS and multiply that resistance with total Capacitance on that node. Sum up such R and C product for all nodes.
In our circuit, there is only one node of interest. That is the driver inverter output, or the end of resistance R. In this case total resistance from the node to VDD/VSS is ‘R’ and total capacitance on the node is ‘aC+2aC=3aC’. Hence the delay can be approximated to be ‘R*3aC= 3aRC’
Now to find out the typical value of fanout ‘a’, we can build a circuit with chain of back to back inverters like following circuit.
Figure 4. Chain of inverters.
Objective is to drive load CL with optimum delay through the chain of inverters. Lets assume the input capacitance of first inverter is ‘C’ as shown in figure with unit width. Fanout being ‘a’ next inverter width would ‘a’ and so forth.
The number of inverters along the path can be represented as a function of CL and C like following.
Total number of inverters along chain D = Loga(CL/C) = ln(CL/C)/ln(a)
Total delay along the chain D = Total inverters along the chain * Delay of each inverter.
Earlier we learned that for a back to back inverters where driver inverter input gate capacitance is ‘C’ and the fanout ration of ‘a’, the delay through driver inverter is 3aRC
Total delay along the chain D = ln(CL/C)/ln(a) * 3aRC
If we want to find the minimum value of total delay function for a specific value of fanout ‘a’, we need to take the derivative of ‘total delay’ with respect to ‘a’ and make it zero. That gives us the minima of the ‘total delay’ with respect to ‘a’.
D = 3*RC*ln(CL/C)*a/ln(a)
dD/da = 3*RC* ln(CL/C) [ (ln(a) -1)/ln2(a)] = 0
Which means : ln(a) = 1, the root of which is a = e.
This is how we derive the fanout of ‘e’ to be an optimal fanout for a chain of inverters.
If one were to plot the value of total delay ‘D’ against ‘a’ for such an inverter chain it looks like following.
Figure 5. Total delay v/s
One more thing to remember here is that, we assumed a chain of inverter. In practice many times you would find a gate driving a long wire. The theory still applies, one just have to find out the effective wire capacitance that the driving gate sees and use that to come up with the fanout ratio.
No comments:
Post a Comment