High-Vt and Low-Vt cells

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High-Vt and Low-Vt cells:

Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices, which have less delay, but leakage is high. The threshold (t) voltage dictates the transistor switching speed, it matters how much minimum threshold voltage applied can make the transistor switching to active state, which results to how fast we can switch the transistor. Disadvantage is it needs to maintain the transistor in a minimum sub threshold voltage level to make it switch fast so it leads to leakage of current in turn loss of power

Effect of Threshold voltage on the propagation delay and transition delay:

look into the below Resistance calculation for NMOS

From above equation we have following points

1. On Resistance of MOS is inversely proportional to the “VDD-VTn” (where VTn is Threshold Voltage).
2. Decreasing the threshold voltage (LOW VTn) increases “VDD-VTn” for constant VDD.
3. Increasing “VDD-VTn” means decreasing “On Resistance” Rn.
4. Decreasing Rn à RC decreases.
5. Means large Driving capability (Ability to source or sink current)
6. Decrease the time to charge the output load (capacitance) (Consists of source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate) **
7. Means “Output Transition time of Gate A” and “Input Transition time for Gate B” decreases.
8. Decreasing the transition time means decreases the propagation time.

Conclusion: 

"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"

Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.

If still you have any confusion below diagram should clarify your doubts.