Minimum pulse width violation: pulse width check

Minimum Pulse width check is important for clocks, for the proper performance of the sequential circuits. This check ensures that, the width of the clock signal, is above a minimum value. Why should the pulse width of a signal shrink ? This is due the unequal rise and fall delays of the combinational cells. Imagine a clock entering a buffer. If the rise delay of the buffer is more than the fall delay, the output clock will have less width than the input. See the following figure, which illustrates the same. So think of, what will happen to the same clock signal, when it passes through a series of same type of buffers. The width of the clock signal keeps decreasing, and at a point when the buffer delay is more than the clock pulse width, the clock pulse gets absorbed. This is known as Pulse absorption. So it is important to perform minimum pulse width check

How to constrain the design for pulse width checks in Primetime?

Keep the variable timing_enable_pulse_clock_constraints to true for enabling the pulse width checks. Define the minimum and maximum required clock pulse width, with the commands set_pulse_clock_min_width and set_pulse_clock_max_width. The result can be seen, after the timing analysis, along with the command report_constraints. If needed, we can ignore the pulse width checks, at particular sequential cells or certain clocks with the command remove_min_pulse_width. How to correct these, if violations are seen ? We need to change the clock tree cells, which have less difference between rise and fall delays. It is always the best to choose the clock tree cells which have minimum delay variations at the begining of your project itself. Then last minute fixes like these can be avoided