Terminology in VLSI

ASIC

Acronym for Application Specific Integrated Circuits. A custom or semi
custom integrated circuit, such as a cell or gate array, created for a specific
application. The complexity of ASICs typically requires significant use of
CAD techniques.

Block

 Also known as functional block or module. Any block within the design
hierarchy instantiated one or more times that will be laid out separately is
referred to as a block module. Block modules are defined divisions of a chip
based on functionality and can be worked on independently of other
functional blocks.

Netlist

 A description of the circuit. The description can be a gate-level or RegisterTransfer
level (RTL) one. It can also be in different languages like Verilog
or VHDL or SPICE.

Physical Design

A portion of a chip or circuit corresponding to a block module that is laid
out separately using a Physical Design tool. It is also referred to as a
physical block, layout region, or layout block.

RTL

 Acronym for Register Transfer Level
Characterization Electrical analysis performed for the purpose of determining typical device
performance characteristics and/or parametric limits.25

CMOS

 Acronym for Complimentary Metal Oxide Semiconductor. An MOS
technology in which both P-channel and N-channel devices are fabricated
on the same die.

Die

 A single square or rectangular piece of silicon into which a specific
semiconductor circuit has been diffused.

Electromigration

 Particle migration in aluminum or copper thin-film or polysilicon
conductors at grain boundaries as a result of high current densities.
Electromigration can lead to either an open circuit condition in a conductor
or a short between adjacent connectors.

Interconnect

The metallization connecting two or more active elements on the surface of
a die; also, the wires connecting the die to the package leads.

Timing Window

Timing window specifies the interval of each circuit node at which a
transition activity is anticipated. For a single clock domain, the time interval
can lie within a clock period. There can be more than one intervals or
overlapping intervals based on complexity of path converging to the node.